1. Field of the Invention
This invention relates to computers. More particularly, it relates to computers having memory cache controllers.
2. Description of the Prior Art
Designers working with the powerful new general-purpose 32-bit microprocessors are finding that coming up with a high-performance system takes more than just a powerful central processor. As they gain experience with 32-bit chips, designers find they must adopt many of the architectural refinements associated with high-performance superminicomputers and mainframes in order to get full performance out of these tiny computing engines. In particular, they are moving to a hierarchical memory scheme in which high-speed cache, or buffer memory, is placed between the microprocessor and main memory to increase a system's throughput.
As better designs whittle away at the miss rate for accessed data--the percentage of times main memory must be read because the data required is not in the cache--they reduce the amount of time the microprocessors must spend in deliberately programmed wait states until memory accesses are completed. Toward this end, a number of semiconductor companies are coming up with chips for cache-based microprocessor systems: special memory parts for building cache buffers and highly integrated cache controller chips, such as the 82385 32-bit cache controller produced by Intel Corporation.
Cache is now seen as a way to take full advantage of the new 32-bit microprocessors, especially in multiple-microprocessor configurations. Without cache, designers must use either commercially available 100-to 120-ns dynamic random-access memories and introduce wait states, or shift to the use of 50- to 60-ns static RAM's, which are much more expensive and also reduce the system's circuit density.
Cache architectures offer a way out of this dilemma by storing the information most frequently accessed from the main memory. In such schemes, the buffer between the microprocessor and the main memory usually consists of the data cache, for storage of the data copied from main memory, and the cache tag memory, which is used to store the memory address locations.
When the microprocessor requests data from memory, the cache controller checks to see whether the address the microprocessor is issuing matches an address found in the cache tag RAM. If it does, the data in the cache data RAM corresponding to the matching cache tag address is sent to the microprocessor. Thus, when the microprocessor tries to read data from the main memory, the high-speed cache will respond first if it has a copy of the requested data. Otherwise, a normal main-memory cycle takes place. In typical systems, data will be supplied by the cache memory more than 90% of the time--that is, the system will have a better than 90% hit rate.
Although the operation of a typical cache is relatively simple in concept, implementation is a complex process involving such factors as the type of memory mapping involved, the cache size, the size of transferred blocks of data, the data-replacement algorithm, and write-request handling. Whereas present circuits are combined with external logic to implement what are called direct-mapped replacement algorithms--in which each memory address maps into the cache at one memory location--the new integrated solutions use more advanced set-associative schemes, in which each address can be mapped into many different locations. And whereas the first allows hit rates from 65% to 90%, depending on the amount of cache memory used and other factors, the advanced solutions allow hit rates in excess of 90%, using one-half to one-fourth the amount of memory space.
A two-way set-associative cache controller for the 80836 from Intel is designated the 82385. It requires 8 Kbits by 32 bits of external SRAM, two address latches, and a data-receiver circuit for bus separation. It can also be used in direct-mapped cache architectures.
Intel's 82385 cache controller will work with the 80386 microprocessor in either a direct-mapped or the two-way set-associative cache configuration.
The 132-pin 82385 contains not only the cache-tag function but a "posted write-through" feature that uses on-board buffers to make information immediately available to an 80386 system bus.
Finally, the 82385 cache controller has features such as bus watching and posted writethrough. The 82385 cache-memory controller, which can store address tags for 32-K bytes of cache memory can run at 16 and 20 MHz.
The cache-tag function acts as a self-initiating directory of what data is being held in SRAM-based cache storage. It automatically checks incoming addresses from hot processors against the data copied in cache from slower dynamic random-access main memory. These specialized address-matching memories can boost system throughput by offloading overhead from a busy host.
The 82385 cache controller fills a need imposed by the ever-faster microprocessors. At 20 MHz, cache memory will become a virtual requirement to realize the full performance capability of the microprocessor. The 82385 stores the address tags for caches of up to 32-K bytes. At 20 MHz, you can use 35-ns SRAM's, which are generally available today.
The cache controller can also monitor the system bus to see what data is changed in main memory and then invalidate corresponding cache data. Using the same technique, it can maintain coherency among several caches in a multiprocessor system.
The 82385 cache controller is a high performance 32-bit peripheral for Intel's 80386 microprocessor. It stores a copy of frequently accessed code and data from main memory in a zero wait state local cache memory. The 82385 enables the 80386 to run at its full potential by reducing the average number of microprocessor wait states to nearly zero. The dual bus architecture of the 82385 allows other masters to access system resources while the 80386 operates locally out of its cache. In this situation, the 82385's "bus watching" mechanism preserves cache coherency by monitoring the system bus address lines at no cost to system or local throughput.
The 82385 is completely software transparent, protecting the integrity of system software. High performance and board savings are achieved because the 82385 integrates a cache directory and all cache management logic on one chip.